1. Field of the Invention
This invention relates to semiconductor storage devices such as dynamic random-access memories (DRAMs) having redundancy circuits for relief from faults, and particularly to semiconductor storage devices in which defect cells are replaced with redundancy cells under testing of memory testers.
2. Description of the Related Art
Conventionally, semiconductor storage devices having large storage capacities such as DRAMs install redundancy circuits for relief from defect cells, which are to be replaced with redundancy cells to improve yields in manufacture. To achieve relief from defect cells by the redundancy circuits, the semiconductor storage devices are placed under tests by memory testers to detect failure addresses in advance, so that the failure addresses are subjected to programming to fuse circuits inside of the redundancy circuits. In normal read/write operations of the semiconductor storage devices, if addresses given from the external match with preprogrammed failure addresses, the semiconductor storage devices are inhibited from selecting regular cells (i.e., defect cells) specified by the failure addresses so that redundancy cells are being selected instead. Thus, it is possible to realize relief from faults by replacing the defect cells with the redundancy cells.
Memory cell arrays such as semiconductor storage devices having multiple-bit configurations (16-bit configurations) realize replacement of defect cells with redundancy cells such that multiple memory cells storing data corresponding to different I/O ports are simultaneously replaced at one time. Suppose a semiconductor storage device which is configured to store 16-bit data DQ0 to DQ15. Herein, consecutive four data are simultaneously subjected to replacement. That is, simultaneous replacement is performed on four data (or four bits) DQ0-DQ3, DQ4-DQ7, DQ8-DQ11 and DQ12-DQ15 respectively.
Generally speaking, the memory testers are used to test functions of the semiconductor memory cells by prescribed operations, as follows:
Data is written to and read from the semiconductor storage device with respect to each of addresses. Then, a check is made as to whether read data matches with an expected value or not. Thus, check results are obtained with respect to all addresses and are then stored in a fail memory of the memory tester. Using data of the check results stored in the fail memory of the memory tester, it is possible to specify failure addresses which fail to perform normal read/write operations.
There are provided two kinds of methods for storing data of check results in the fail memory of the memory tester, which will be described with reference to FIGS. 8 and 9.
That is, FIG. 8 shows a first method in which a data check unit 401 provided inside of a memory tester 400 performs checking as to whether 16-bit data DQ0-DQ15 output from a semiconductor storage device 300, which is a tested subject, match with expected values or not. Thus, the data check unit 401 obtains check results with respect to all bits, so that the check results are stored in a fail memory 402 within the memory tester 400 as its test results.
FIG. 9 shows a second method in which as similar to the first method, a data check unit 411 provided inside of a memory tester 410 performs checking on 16-bit data DQ0-DQ1 output from a semiconductor storage device 300, so that check results are produced with respect to all bits. The check results are subjected to compression by a data compression unit 412 and are then stored in a fail memory 413 within the memory tester 410. As described before, simultaneous replacement for replacing plural defect cells with plural redundancy cells is performed by a redundancy circuit with respect to plural data, namely four bits such as DQ0-DQ3. Herein, it is needless to recognize which of the four bits actually fails within the prescribed four bits. In other words, it is sufficient to recognize that a fault occurs on any one of the prescribed four bits. For this reason, the data compression unit 412 performs compression by each unit of plural bits which are simultaneously placed under replacement by the redundancy circuit. Thus, it is possible to obtain necessary and sufficient information for relief from defect cells. As compared with the first method shown in FIG. 8, the second method shown in FIG. 9 is advantageous in that a capacity of the fail memory can be reduced.
According to the conventional technology, however, the aforementioned semiconductor storage device directly outputs multiple-bit data (e.g., DQ0-DQ15), regardless of a number of bits being placed under replacement by the redundancy circuit. This causes a problem in that manufacturer needs capital investment to facilitate developments and improvements of memory testers in response to increases of semiconductor storage devices in scale and capacity.
In the case of FIG. 8, for example, it is necessary to store in the fail memory 402 all the check results which are produced by the data check unit 401 with respect to all bits DQ0-DQ15 output from the semiconductor storage device 300. This requires an extension of the fail memory 402 in capacity in response to an increase of the semiconductor storage device 300 in scale and capacity. In the case of FIG. 9, the memory tester 410 is designed to compress the check results which are produced by the data check unit 411 with respect to all bits DQ0-DQ15 output from the semiconductor storage device 300. Hence, it is necessary to provide the memory tester 410 with data compression functions (namely, data compression unit 412).
It is an object of the invention to provide a semiconductor storage device that is capable of producing data used for checking defectiveness to specify defect cells being replaced with redundancy cells without arranging capital investment on memory testers to develop and improve functions.
This invention provides a semiconductor storage device such as a DRAM which is configured to enable testing on defectiveness of memory cells by an existing memory tester, which locates defect cells to be replaced with redundancy cells by a redundancy circuit. Herein, a write circuit writes multiple-bit data to memory cells of a memory cell array under testing. Then, the multiple-bit data are read from the memory cell array by a read circuit and are compared with original one to make decisions of xe2x80x9cpassxe2x80x9d or xe2x80x9cfailxe2x80x9d on the memory cells by the memory tester. Specifically, the read circuit is configured by plural pairs of a data output circuit and a data compression circuit with respect to plural sets of prescribed data constructing the multiple-bit data read from the memory cell array. For example, the multiple-bit data consists of sixteen bits (DQ0-DQ15) while each prescribed data consists of four bits (e.g., DQ0-DQ3) corresponding to prescribed memory cells which are subjected to simultaneous replacement.
The data compression circuit is configured by an exclusive-or circuit that compresses the prescribed data to specific data having a specific logical value if the prescribed data has a prescribed data pattern. Or, the data compression circuit is configured using two exclusive-or circuits that compress different types of the prescribed data to specific data. Namely, a first exclusive-or circuit compresses a first type of the prescribed data whose bits are all set to a same logical value to the specific data, while a second exclusive-or circuit compresses a second type of the prescribed data consisting of bits corresponding to a combination of different logical values to the specific data.
The specific data is forwarded as single-bit data (e.g., DQ0) within the prescribed data which are read from the memory cell array. Using the specific data, the existing memory tester is capable of easily making decisions of xe2x80x9cpassxe2x80x9d or xe2x80x9cfailxe2x80x9d on the memory cells corresponding to bits of the prescribed data being read out.